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io4414.h

00001 /* Copyright (c) 2002, Marek Michalkiewicz
00002    All rights reserved.
00003 
00004    Redistribution and use in source and binary forms, with or without
00005    modification, are permitted provided that the following conditions are met:
00006 
00007    * Redistributions of source code must retain the above copyright
00008      notice, this list of conditions and the following disclaimer.
00009    * Redistributions in binary form must reproduce the above copyright
00010      notice, this list of conditions and the following disclaimer in
00011      the documentation and/or other materials provided with the
00012      distribution.
00013 
00014   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00015   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00016   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00017   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00018   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00019   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00020   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00021   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00022   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00023   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00024   POSSIBILITY OF SUCH DAMAGE. */
00025 
00026 /* avr/io4414.h - definitions for AT90S4414 */
00027 
00028 #ifndef _AVR_IO4414_H_
00029 #define _AVR_IO4414_H_ 1
00030 
00031 /* This file should only be included from <avr/io.h>, never directly. */
00032 
00033 #ifndef _AVR_IO_H_
00034 #  error "Include <avr/io.h> instead of this file."
00035 #endif
00036 
00037 #ifndef _AVR_IOXXX_H_
00038 #  define _AVR_IOXXX_H_ "io4414.h"
00039 #else
00040 #  error "Attempt to include more than one <avr/ioXXX.h> file."
00041 #endif 
00042 
00043 #include <avr/sfr_defs.h>
00044 
00045 /* I/O registers */
00046 
00047 /* Analog Comparator Control and Status Register */
00048 #define ACSR    _SFR_IO8(0x08)
00049 
00050 /* UART Baud Rate Register */
00051 #define UBRR    _SFR_IO8(0x09)
00052 
00053 /* UART Control Register */
00054 #define UCR     _SFR_IO8(0x0A)
00055 
00056 /* UART Status Register */
00057 #define USR     _SFR_IO8(0x0B)
00058 
00059 /* UART I/O Data Register */
00060 #define UDR     _SFR_IO8(0x0C)
00061 
00062 /* SPI Control Register */
00063 #define SPCR    _SFR_IO8(0x0D)
00064 
00065 /* SPI Status Register */
00066 #define SPSR    _SFR_IO8(0x0E)
00067 
00068 /* SPI I/O Data Register */
00069 #define SPDR    _SFR_IO8(0x0F)
00070 
00071 /* Input Pins, Port D */
00072 #define PIND    _SFR_IO8(0x10)
00073 
00074 /* Data Direction Register, Port D */
00075 #define DDRD    _SFR_IO8(0x11)
00076 
00077 /* Data Register, Port D */
00078 #define PORTD   _SFR_IO8(0x12)
00079 
00080 /* Input Pins, Port C */
00081 #define PINC    _SFR_IO8(0x13)
00082 
00083 /* Data Direction Register, Port C */
00084 #define DDRC    _SFR_IO8(0x14)
00085 
00086 /* Data Register, Port C */
00087 #define PORTC   _SFR_IO8(0x15)
00088 
00089 /* Input Pins, Port B */
00090 #define PINB    _SFR_IO8(0x16)
00091 
00092 /* Data Direction Register, Port B */
00093 #define DDRB    _SFR_IO8(0x17)
00094 
00095 /* Data Register, Port B */
00096 #define PORTB   _SFR_IO8(0x18)
00097 
00098 /* Input Pins, Port A */
00099 #define PINA    _SFR_IO8(0x19)
00100 
00101 /* Data Direction Register, Port A */
00102 #define DDRA    _SFR_IO8(0x1A)
00103 
00104 /* Data Register, Port A */
00105 #define PORTA   _SFR_IO8(0x1B)
00106 
00107 /* EEPROM Control Register */
00108 #define EECR    _SFR_IO8(0x1C)
00109 
00110 /* EEPROM Data Register */
00111 #define EEDR    _SFR_IO8(0x1D)
00112 
00113 /* EEPROM Address Register */
00114 #define EEAR    _SFR_IO16(0x1E)
00115 #define EEARL   _SFR_IO8(0x1E)
00116 #define EEARH   _SFR_IO8(0x1F)
00117 
00118 /* Watchdog Timer Control Register */
00119 #define WDTCR   _SFR_IO8(0x21)
00120 
00121 /* T/C 1 Input Capture Register */
00122 #define ICR1    _SFR_IO16(0x24)
00123 #define ICR1L   _SFR_IO8(0x24)
00124 #define ICR1H   _SFR_IO8(0x25)
00125 
00126 /* Timer/Counter1 Output Compare Register B */
00127 #define OCR1B   _SFR_IO16(0x28)
00128 #define OCR1BL  _SFR_IO8(0x28)
00129 #define OCR1BH  _SFR_IO8(0x29)
00130 
00131 /* Timer/Counter1 Output Compare Register A */
00132 #define OCR1A   _SFR_IO16(0x2A)
00133 #define OCR1AL  _SFR_IO8(0x2A)
00134 #define OCR1AH  _SFR_IO8(0x2B)
00135 
00136 /* Timer/Counter 1 */
00137 #define TCNT1   _SFR_IO16(0x2C)
00138 #define TCNT1L  _SFR_IO8(0x2C)
00139 #define TCNT1H  _SFR_IO8(0x2D)
00140 
00141 /* Timer/Counter 1 Control and Status Register */
00142 #define TCCR1B  _SFR_IO8(0x2E)
00143 
00144 /* Timer/Counter 1 Control Register */
00145 #define TCCR1A  _SFR_IO8(0x2F)
00146 
00147 /* Timer/Counter 0 */
00148 #define TCNT0   _SFR_IO8(0x32)
00149 
00150 /* Timer/Counter 0 Control Register */
00151 #define TCCR0   _SFR_IO8(0x33)
00152 
00153 /* MCU general Control Register */
00154 #define MCUCR   _SFR_IO8(0x35)
00155 
00156 /* Timer/Counter Interrupt Flag register */
00157 #define TIFR    _SFR_IO8(0x38)
00158 
00159 /* Timer/Counter Interrupt MaSK register */
00160 #define TIMSK   _SFR_IO8(0x39)
00161 
00162 /* General Interrupt Flag Register */
00163 #define GIFR   _SFR_IO8(0x3A)
00164 
00165 /* General Interrupt MaSK register */
00166 #define GIMSK   _SFR_IO8(0x3B)
00167 
00168 /* Stack Pointer */
00169 #define SP      _SFR_IO16(0x3D)
00170 #define SPL     _SFR_IO8(0x3D)
00171 #define SPH     _SFR_IO8(0x3E)
00172 
00173 /* Status REGister */
00174 #define SREG    _SFR_IO8(0x3F)
00175 
00176 /* Interrupt vectors */
00177 
00178 #define SIG_INTERRUPT0          _VECTOR(1)
00179 #define SIG_INTERRUPT1          _VECTOR(2)
00180 #define SIG_INPUT_CAPTURE1      _VECTOR(3)
00181 #define SIG_OUTPUT_COMPARE1A    _VECTOR(4)
00182 #define SIG_OUTPUT_COMPARE1B    _VECTOR(5)
00183 #define SIG_OVERFLOW1           _VECTOR(6)
00184 #define SIG_OVERFLOW0           _VECTOR(7)
00185 #define SIG_SPI                 _VECTOR(8)
00186 #define SIG_UART_RECV           _VECTOR(9)
00187 #define SIG_UART_DATA           _VECTOR(10)
00188 #define SIG_UART_TRANS          _VECTOR(11)
00189 #define SIG_COMPARATOR          _VECTOR(12)
00190 
00191 #define _VECTORS_SIZE 26
00192 
00193 /*
00194    The Register Bit names are represented by their bit number (0-7).
00195 */
00196 
00197 /* General Interrupt MaSK register */
00198 #define    INT1         7
00199 #define    INT0         6
00200 
00201 /* General Interrupt Flag Register */
00202 #define    INTF1        7
00203 #define    INTF0        6
00204 
00205 /* Timer/Counter Interrupt MaSK register */
00206 #define    TOIE1        7
00207 #define    OCIE1A       6
00208 #define    OCIE1B       5
00209 #define    TICIE1       3
00210 #define    TOIE0        1
00211 
00212 /* Timer/Counter Interrupt Flag register */
00213 #define    TOV1         7
00214 #define    OCF1A        6
00215 #define    OCF1B        5
00216 #define    ICF1         3
00217 #define    TOV0         1
00218 
00219 /* MCU general Control Register */
00220 #define    SRE          7
00221 #define    SRW          6
00222 #define    SE           5
00223 #define    SM           4
00224 #define    ISC11        3
00225 #define    ISC10        2
00226 #define    ISC01        1
00227 #define    ISC00        0
00228 
00229 /* Timer/Counter 0 Control Register */
00230 #define    CS02         2
00231 #define    CS01         1
00232 #define    CS00         0
00233 
00234 /* Timer/Counter 1 Control Register */
00235 #define    COM1A1       7
00236 #define    COM1A0       6
00237 #define    COM1B1       5
00238 #define    COM1B0       4
00239 #define    PWM11        1
00240 #define    PWM10        0
00241 
00242 /* Timer/Counter 1 Control and Status Register */
00243 #define    ICNC1        7
00244 #define    ICES1        6
00245 #define    CTC1         3
00246 #define    CS12         2
00247 #define    CS11         1
00248 #define    CS10         0
00249 
00250 /* Watchdog Timer Control Register */
00251 #define    WDTOE        4
00252 #define    WDE          3
00253 #define    WDP2         2
00254 #define    WDP1         1
00255 #define    WDP0         0
00256 
00257 /* EEPROM Control Register */
00258 #define    EEMWE        2
00259 #define    EEWE         1
00260 #define    EERE         0
00261 
00262 /* Data Register, Port A */
00263 #define    PA7          7
00264 #define    PA6          6
00265 #define    PA5          5
00266 #define    PA4          4
00267 #define    PA3          3
00268 #define    PA2          2
00269 #define    PA1          1
00270 #define    PA0          0
00271 
00272 /* Data Direction Register, Port A */
00273 #define    DDA7         7
00274 #define    DDA6         6
00275 #define    DDA5         5
00276 #define    DDA4         4
00277 #define    DDA3         3
00278 #define    DDA2         2
00279 #define    DDA1         1
00280 #define    DDA0         0
00281 
00282 /* Input Pins, Port A */
00283 #define    PINA7        7
00284 #define    PINA6        6
00285 #define    PINA5        5
00286 #define    PINA4        4
00287 #define    PINA3        3
00288 #define    PINA2        2
00289 #define    PINA1        1
00290 #define    PINA0        0
00291 
00292 /* Data Register, Port B */
00293 #define    PB7          7
00294 #define    PB6          6
00295 #define    PB5          5
00296 #define    PB4          4
00297 #define    PB3          3
00298 #define    PB2          2
00299 #define    PB1          1
00300 #define    PB0          0
00301 
00302 /* Data Direction Register, Port B */
00303 #define    DDB7         7
00304 #define    DDB6         6
00305 #define    DDB5         5
00306 #define    DDB4         4
00307 #define    DDB3         3
00308 #define    DDB2         2
00309 #define    DDB1         1
00310 #define    DDB0         0
00311 
00312 /* Input Pins, Port B */
00313 #define    PINB7        7
00314 #define    PINB6        6
00315 #define    PINB5        5
00316 #define    PINB4        4
00317 #define    PINB3        3
00318 #define    PINB2        2
00319 #define    PINB1        1
00320 #define    PINB0        0
00321 
00322 /* Data Register, Port C */
00323 #define    PC7          7
00324 #define    PC6          6
00325 #define    PC5          5
00326 #define    PC4          4
00327 #define    PC3          3
00328 #define    PC2          2
00329 #define    PC1          1
00330 #define    PC0          0
00331 
00332 /* Data Direction Register, Port C */
00333 #define    DDC7         7
00334 #define    DDC6         6
00335 #define    DDC5         5
00336 #define    DDC4         4
00337 #define    DDC3         3
00338 #define    DDC2         2
00339 #define    DDC1         1
00340 #define    DDC0         0
00341 
00342 /* Input Pins, Port C */
00343 #define    PINC7        7
00344 #define    PINC6        6
00345 #define    PINC5        5
00346 #define    PINC4        4
00347 #define    PINC3        3
00348 #define    PINC2        2
00349 #define    PINC1        1
00350 #define    PINC0        0
00351 
00352 /* Data Register, Port D */
00353 #define    PD7          7
00354 #define    PD6          6
00355 #define    PD5          5
00356 #define    PD4          4
00357 #define    PD3          3
00358 #define    PD2          2
00359 #define    PD1          1
00360 #define    PD0          0
00361 
00362 /* Data Direction Register, Port D */
00363 #define    DDD7         7
00364 #define    DDD6         6
00365 #define    DDD5         5
00366 #define    DDD4         4
00367 #define    DDD3         3
00368 #define    DDD2         2
00369 #define    DDD1         1
00370 #define    DDD0         0
00371 
00372 /* Input Pins, Port D */
00373 #define    PIND7        7
00374 #define    PIND6        6
00375 #define    PIND5        5
00376 #define    PIND4        4
00377 #define    PIND3        3
00378 #define    PIND2        2
00379 #define    PIND1        1
00380 #define    PIND0        0
00381 
00382 /* SPI Status Register */
00383 #define    SPIF         7
00384 #define    WCOL         6
00385 
00386 /* SPI Control Register */
00387 #define    SPIE         7
00388 #define    SPE          6
00389 #define    DORD         5
00390 #define    MSTR         4
00391 #define    CPOL         3
00392 #define    CPHA         2
00393 #define    SPR1         1
00394 #define    SPR0         0
00395 
00396 /* UART Status Register */
00397 #define    RXC          7
00398 #define    TXC          6
00399 #define    UDRE         5
00400 #define    FE           4
00401 #define    DOR          3
00402 
00403 /* UART Control Register */
00404 #define    RXCIE        7
00405 #define    TXCIE        6
00406 #define    UDRIE        5
00407 #define    RXEN         4
00408 #define    TXEN         3
00409 #define    CHR9         2
00410 #define    RXB8         1
00411 #define    TXB8         0
00412 
00413 /* Analog Comparator Control and Status Register */
00414 #define    ACD          7
00415 #define    ACO          5
00416 #define    ACI          4
00417 #define    ACIE         3
00418 #define    ACIC         2
00419 #define    ACIS1        1
00420 #define    ACIS0        0
00421 
00422 /* Pointer definition   */
00423 #define    XL           r26
00424 #define    XH           r27
00425 #define    YL           r28
00426 #define    YH           r29
00427 #define    ZL           r30
00428 #define    ZH           r31
00429 
00430 /* Constants        */
00431 #define    RAMEND       0x15F    /* Last On-Chip SRAM Location */
00432 #define    XRAMEND      0xFFFF
00433 #define    E2END        0xFF
00434 #define    FLASHEND     0xFFF
00435 
00436 #endif /* _AVR_IO4414_H_ */

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