Xilinx Design Summary

FLASH_TEST Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	54	3,840	1%
Number of 4 input LUTs	66	3,840	1%
Logic Distribution
Number of occupied Slices	62	1,920	3%
Number of Slices containing only related logic	62	62	100%
Number of Slices containing unrelated logic	0	62	0%
Total Number of 4 input LUTs	109	3,840	2%
Number used as logic	66
Number used as a route-thru	43
Number of bonded IOBs	59	97	60%
IOB Flip Flops	40
Number of GCLKs	1	8	12%
Total equivalent gate count for design	1,478
Additional JTAG gate count for IOBs	2,832

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met