SDRAM_TEST Project Status
Project File: SDRAM_test.ise Current State: Programming File Generated
Module Name: test_board
  • Errors:
No Errors
Target Device: xc3s200-5tq144
  • Warnings:
32 Warnings (0 new, 0 filtered)
Product Version: ISE, 8.1i
  • Updated:
Wt 31. lip 14:24:01 2007
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 251 3,840 6%  
Number of 4 input LUTs 427 3,840 11%  
Logic Distribution    
Number of occupied Slices 340 1,920 17%  
Number of Slices containing only related logic 340 340 100%  
Number of Slices containing unrelated logic 0 340 0%  
Total Number 4 input LUTs 577 3,840 15%  
Number used as logic 427      
Number used as a route-thru 149      
Number used as Shift registers 1      
Number of bonded IOBs 71 97 73%  
IOB Flip Flops 59      
Number of GCLKs 1 8 12%  
Number of DCMs 2 4 50%  
Total equivalent gate count for design 20,348      
Additional JTAG gate count for IOBs 3,408      
 
Performance Summary
Final Timing Score: 320 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: 1 Failing Constraint    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWt 31. lip 14:23:04 2007027 Warnings (0 new, 0 filtered)4 Infos (1 new, 0 filtered)
Translation ReportCurrentWt 31. lip 14:23:12 2007004 Infos (0 new, 0 filtered)
Map ReportCurrentWt 31. lip 14:23:19 200704 Warnings (0 new, 0 filtered)3 Infos (0 new, 0 filtered)
Place and Route ReportCurrentWt 31. lip 14:23:41 200701 Warning (0 new, 0 filtered)1 Info (1 new, 0 filtered)
Static Timing ReportCurrentWt 31. lip 14:23:47 2007001 Info (0 new, 0 filtered)
Bitgen ReportCurrentWt 31. lip 14:24:01 2007000