FLASH_TEST Project Status | |||
Project File: | flash_test.ise | Current State: | Programming File Generated |
Module Name: | flash_test |
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No Errors |
Target Device: | xc3s200-5tq144 |
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35 Warnings |
Product Version: | ISE 9.1i |
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Cz 16. sie 16:03:41 2007 |
FLASH_TEST Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 54 | 3,840 | 1% | |
Number of 4 input LUTs | 66 | 3,840 | 1% | |
Logic Distribution | ||||
Number of occupied Slices | 62 | 1,920 | 3% | |
Number of Slices containing only related logic | 62 | 62 | 100% | |
Number of Slices containing unrelated logic | 0 | 62 | 0% | |
Total Number of 4 input LUTs | 109 | 3,840 | 2% | |
Number used as logic | 66 | |||
Number used as a route-thru | 43 | |||
Number of bonded IOBs | 59 | 97 | 60% | |
IOB Flip Flops | 40 | |||
Number of GCLKs | 1 | 8 | 12% | |
Total equivalent gate count for design | 1,478 | |||
Additional JTAG gate count for IOBs | 2,832 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Cz 16. sie 16:02:33 2007 | 0 | 33 Warnings | 9 Infos |
Translation Report | Current | Cz 16. sie 16:02:47 2007 | 0 | 0 | 0 |
Map Report | Current | Cz 16. sie 16:02:59 2007 | 0 | 1 Warning | 3 Infos |
Place and Route Report | Current | Cz 16. sie 16:03:19 2007 | 0 | 1 Warning | 2 Infos |
Static Timing Report | Current | Cz 16. sie 16:03:27 2007 | 0 | 0 | 3 Infos |
Bitgen Report | Current | Cz 16. sie 16:03:40 2007 | 0 | 0 | 0 |