SDRAM_TEST Project Status | |||
Project File: | SDRAM_test.ise | Current State: | Programming File Generated |
Module Name: | test_board |
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No Errors |
Target Device: | xc3s200-5tq144 |
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32 Warnings (0 new, 0 filtered) |
Product Version: | ISE, 8.1i |
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Wt 31. lip 14:24:01 2007 |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 251 | 3,840 | 6% | |
Number of 4 input LUTs | 427 | 3,840 | 11% | |
Logic Distribution | ||||
Number of occupied Slices | 340 | 1,920 | 17% | |
Number of Slices containing only related logic | 340 | 340 | 100% | |
Number of Slices containing unrelated logic | 0 | 340 | 0% | |
Total Number 4 input LUTs | 577 | 3,840 | 15% | |
Number used as logic | 427 | |||
Number used as a route-thru | 149 | |||
Number used as Shift registers | 1 | |||
Number of bonded IOBs | 71 | 97 | 73% | |
IOB Flip Flops | 59 | |||
Number of GCLKs | 1 | 8 | 12% | |
Number of DCMs | 2 | 4 | 50% | |
Total equivalent gate count for design | 20,348 | |||
Additional JTAG gate count for IOBs | 3,408 |
Performance Summary | |||
Final Timing Score: | 320 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | 1 Failing Constraint |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Wt 31. lip 14:23:04 2007 | 0 | 27 Warnings (0 new, 0 filtered) | 4 Infos (1 new, 0 filtered) |
Translation Report | Current | Wt 31. lip 14:23:12 2007 | 0 | 0 | 4 Infos (0 new, 0 filtered) |
Map Report | Current | Wt 31. lip 14:23:19 2007 | 0 | 4 Warnings (0 new, 0 filtered) | 3 Infos (0 new, 0 filtered) |
Place and Route Report | Current | Wt 31. lip 14:23:41 2007 | 0 | 1 Warning (0 new, 0 filtered) | 1 Info (1 new, 0 filtered) |
Static Timing Report | Current | Wt 31. lip 14:23:47 2007 | 0 | 0 | 1 Info (0 new, 0 filtered) |
Bitgen Report | Current | Wt 31. lip 14:24:01 2007 | 0 | 0 | 0 |