TEST_2 Project Status
Project File: Test_2.ise Current State: Programming File Generated
Module Name: Test_2
  • Errors:
No Errors
Target Device: xc3s200-5tq144
  • Warnings:
No Warnings
Product Version: ISE, 8.1i
  • Updated:
?r 11. lip 08:28:39 2007
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 27 3,840 1%  
Number of 4 input LUTs 35 3,840 1%  
Logic Distribution    
Number of occupied Slices 44 1,920 2%  
Number of Slices containing only related logic 44 44 100%  
Number of Slices containing unrelated logic 0 44 0%  
Total Number 4 input LUTs 85 3,840 2%  
Number used as logic 35      
Number used as a route-thru 50      
Number of bonded IOBs 3 97 3%  
IOB Flip Flops 1      
Number of GCLKs 1 8 12%  
Total equivalent gate count for design 758      
Additional JTAG gate count for IOBs 144      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent?r 11. lip 08:28:09 2007000
Translation ReportCurrent?r 11. lip 08:28:15 2007002 Infos
Map ReportCurrent?r 11. lip 08:28:19 2007003 Infos
Place and Route ReportCurrent?r 11. lip 08:28:27 2007002 Infos
Static Timing ReportCurrent?r 11. lip 08:28:31 2007002 Infos
Bitgen ReportCurrent?r 11. lip 08:28:39 2007000