TEST_2 Project Status | |||
Project File: | Test_2.ise | Current State: | Programming File Generated |
Module Name: | Test_2 |
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No Errors |
Target Device: | xc3s200-5tq144 |
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No Warnings |
Product Version: | ISE, 8.1i |
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?r 11. lip 08:28:39 2007 |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 27 | 3,840 | 1% | |
Number of 4 input LUTs | 35 | 3,840 | 1% | |
Logic Distribution | ||||
Number of occupied Slices | 44 | 1,920 | 2% | |
Number of Slices containing only related logic | 44 | 44 | 100% | |
Number of Slices containing unrelated logic | 0 | 44 | 0% | |
Total Number 4 input LUTs | 85 | 3,840 | 2% | |
Number used as logic | 35 | |||
Number used as a route-thru | 50 | |||
Number of bonded IOBs | 3 | 97 | 3% | |
IOB Flip Flops | 1 | |||
Number of GCLKs | 1 | 8 | 12% | |
Total equivalent gate count for design | 758 | |||
Additional JTAG gate count for IOBs | 144 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | ?r 11. lip 08:28:09 2007 | 0 | 0 | 0 |
Translation Report | Current | ?r 11. lip 08:28:15 2007 | 0 | 0 | 2 Infos |
Map Report | Current | ?r 11. lip 08:28:19 2007 | 0 | 0 | 3 Infos |
Place and Route Report | Current | ?r 11. lip 08:28:27 2007 | 0 | 0 | 2 Infos |
Static Timing Report | Current | ?r 11. lip 08:28:31 2007 | 0 | 0 | 2 Infos |
Bitgen Report | Current | ?r 11. lip 08:28:39 2007 | 0 | 0 | 0 |