LCD Project Status
Project File: LCD.ise Current State: Programming File Generated
Module Name: LCD
  • Errors:
No Errors
Target Device: xc3s200-5tq144
  • Warnings:
2 Warnings
Product Version: ISE, 8.1i
  • Updated:
Cz 12. lip 09:12:06 2007
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 67 3,840 1%  
Number of 4 input LUTs 217 3,840 5%  
Logic Distribution    
Number of occupied Slices 141 1,920 7%  
Number of Slices containing only related logic 141 141 100%  
Number of Slices containing unrelated logic 0 141 0%  
Total Number 4 input LUTs 247 3,840 6%  
Number used as logic 217      
Number used as a route-thru 30      
Number of bonded IOBs 8 97 8%  
IOB Flip Flops 1      
Number of GCLKs 2 8 25%  
Total equivalent gate count for design 2,062      
Additional JTAG gate count for IOBs 384      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentCz 12. lip 08:32:06 20070018 Infos
Translation ReportCurrentCz 12. lip 08:32:12 2007002 Infos
Map ReportCurrentCz 12. lip 08:32:17 200701 Warning3 Infos
Place and Route ReportCurrentCz 12. lip 08:32:29 200701 Warning2 Infos
Static Timing ReportCurrentCz 12. lip 08:32:33 2007002 Infos
Bitgen ReportCurrentCz 12. lip 08:32:41 2007000