VGA_RAM Project Status | |||
Project File: | VGA_RAM.ise | Current State: | Programming File Generated |
Module Name: | VGA_RAM |
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No Errors |
Target Device: | xc3s200-5tq144 |
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6 Warnings |
Product Version: | ISE, 8.1i |
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Wt 17. lip 09:02:12 2007 |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 87 | 3,840 | 2% | |
Number of 4 input LUTs | 261 | 3,840 | 6% | |
Logic Distribution | ||||
Number of occupied Slices | 160 | 1,920 | 8% | |
Number of Slices containing only related logic | 160 | 160 | 100% | |
Number of Slices containing unrelated logic | 0 | 160 | 0% | |
Total Number 4 input LUTs | 299 | 3,840 | 7% | |
Number used as logic | 261 | |||
Number used as a route-thru | 38 | |||
Number of bonded IOBs | 17 | 97 | 17% | |
IOB Flip Flops | 2 | |||
Number of Block RAMs | 8 | 12 | 66% | |
Number of GCLKs | 3 | 8 | 37% | |
Total equivalent gate count for design | 527,034 | |||
Additional JTAG gate count for IOBs | 816 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Pt 13. lip 13:50:33 2007 | 0 | 2 Warnings | 2 Infos |
Translation Report | Current | Pt 13. lip 13:50:39 2007 | 0 | 0 | 3 Infos |
Map Report | Current | Pt 13. lip 13:50:44 2007 | 0 | 2 Warnings | 3 Infos |
Place and Route Report | Current | Pt 13. lip 13:50:55 2007 | 0 | 2 Warnings | 2 Infos |
Static Timing Report | Current | Pt 13. lip 13:50:59 2007 | 0 | 0 | 2 Infos |
Bitgen Report | Current | Pt 13. lip 13:51:10 2007 | 0 | 0 | 0 |