VGA_RAM Project Status | |||
Project File: | VGA_RAM.ise | Current State: | Programming File Generated |
Module Name: | VGA_RAM |
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No Errors |
Target Device: | xc3s200-5tq144 |
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3 Warnings |
Product Version: | ISE, 8.1i |
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Wt 17. lip 09:01:33 2007 |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 46 | 3,840 | 1% | |
Number of 4 input LUTs | 133 | 3,840 | 3% | |
Logic Distribution | ||||
Number of occupied Slices | 75 | 1,920 | 3% | |
Number of Slices containing only related logic | 75 | 75 | 100% | |
Number of Slices containing unrelated logic | 0 | 75 | 0% | |
Total Number of 4 input LUTs | 133 | 3,840 | 3% | |
Number of bonded IOBs | 13 | 97 | 13% | |
IOB Flip Flops | 2 | |||
Number of Block RAMs | 8 | 12 | 66% | |
Number of GCLKs | 2 | 8 | 25% | |
Total equivalent gate count for design | 525,488 | |||
Additional JTAG gate count for IOBs | 624 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Pt 13. lip 16:15:00 2007 | 0 | 1 Warning | 1 Info |
Translation Report | Current | Pt 13. lip 16:15:06 2007 | 0 | 0 | 3 Infos |
Map Report | Current | Pt 13. lip 16:15:11 2007 | 0 | 1 Warning | 3 Infos |
Place and Route Report | Current | Pt 13. lip 16:15:21 2007 | 0 | 1 Warning | 2 Infos |
Static Timing Report | Current | Pt 13. lip 16:15:25 2007 | 0 | 0 | 2 Infos |
Bitgen Report | Current | Pt 13. lip 16:15:35 2007 | 0 | 0 | 0 |